                     Release Note for BCM5703 BOOT Code Firmware
                    ==================================================
Version 2.29: 
	1. Fixed PXE ROM size bug

Version 2.28:
    1. Fixed configuration read bug. 

Version 2.27:
    1. Supports Shared Memory data structure version 1
    2. Removed phase 2 image loading failure LED blink feature (to save space)

Version 2.26:
    1. Support WoL Limit 10 speed
    2. Added 2nd phase signature.

Version 2.25:
    1. Changed NVRAM corruption workaround algorithm

Version 2.24:
    1. Reversed the NVRAM corruption workaround algorithm to old method

Version 2.23:
    1. Use default MAC address for entry 1 to 15
    2. Changed NVRAM corruption workaround algorithm

Version 2.22:
    1. Supports dynamic bootcode location (no longer need to be in a 
       fixed address in NVM).
    2. Implemented a new WOL scheme that requires drivers released
       after 07/17/02. Legacy drivers will continue to behave according 
       to the old scheme.
    3. Added power saving mode support.
    4. Minor bug fixes/enhancements for various corner cases:
       a. Fixed a bug where bootcode may fail to cut auxiliary power 
          when WOL is disabled on some NICs.
       b. Propagate EEPROM setting regarding WOL even on device reset.
       c. Fixed a problem where system locks up if PXE is enabled.
       d. Fixed timing in propagating ASF configuration to driver.
       e. When enabled, restore WOL after loading and/or unloading PXE 
          or DOS driver.
       f. Fixed an LED problem with A2 LOM when ASF is enabled.
       g. Eliminated potential PHY access contention with driver.
       h. Added prevention on potential flash/EEPROM corruption if chip
          operates under an invalid voltage range.
       i. Fixed ASF configuration application misleading EEPROM content
          problem.
    5. Program all MacAddr Registers with the MacAddress in NVRAM

Version 2.21a:
    1. Fixed intermittent chip CPU crashing in auxiliary power mode 
         (CQ#3763).

Version 2.21:
    1. Propagate GPIO_1 usage to driver and corrected the usage
       in a VPD operation.
    2. Updated LED modes of operations.

Version 2.19:
    1. Exploited power state and pci power presence features supported
       in A2.
    2. Included write protect of EEPROM for some LOM design.
    3. Increased the bootcode image size to 5kbytes (5120 bytes).
    4. Fixed pxe speed initialization (CQ#3488).
    5. Restored range check for VPD access.

Version 2.18:
    1. Support fastboot initiative.
    2. PXE and ASF no longer need to be mutually exclusive.
    3. Updated Ethernet@WireSpeed setup sequence.

Version 2.17:
    1. Employed block read method when loading other firmwares (e.g. ASF)
       from non-volatile memory.
    2. Increased the bootcode image size to 4.5kbytes (4608 bytes). This
       may have impact on boards that already have pxe or other firmware
       programmed as they need to be reprogrammed.
    3. Added CRC checking before loading phase 2 bootcode. All speed LEDs
       will light up when CRC check fails.
    4. Added CRC checking before loading other firmware (e.g. ASF). All 
       speed LEDs will light up when CRC check fails (CQ#3259).
    5. Fixed a bug where a system cannot boot up if phase 2 bootcode is
       corrupted.
    6. Fixed a bug where Windows does not wake up from standby due to
       bootcode cutting off aux power.
    7. Eliminated flash interface reset as this may cause non-volatile
       memory module to become out of sync.
    8. Corrected expansion ROM address to dword aligned, eliminating
       lockup during expansiom ROM service through PCI-X (CQ#3259).
    9. Added Ethernet@WireSpeed support.
   10. Uses 0x16A6 as the new device ID in the boot image.

Version 2.16:
    1. Employed block read method when loading codes from non-volatile
       memory.

Version 2.15: (A0 chip is no longer supported)
    1. Speed up the PXE loading (CQ#3108).
    2. Enable expansion ROM bit in phase one booting to avoid BIOS missing
       to load PXE when enabled.
    3. Implemented two-phase loading to speed up the boot process.
    4. Firmware stops running after loading ASF to avoid interference.
    5. Use software arbitration support by the hardware when accessing 
       non-volatile memory.
    6. Included cold WOL support.
    7. Fixed a problem where the system fails to boot when both PXE and
       WOL are enabled (CQ#2977).
    8. Fixed a bug where the firmware did not clear VPD request after
       it is serviced.

Version 2.14:
    1. Moved multiple boot agent codes and fixed uninitialized variable bug.
    2. Updated default subsystem device ID.
    3. Temporarily remove cold WOL support to ensure proper bootcode execution.

Version 2.13:
    1. Added new GPIO sequences for WOL.
    2. Added cold WOL support.
    3. Embedded version string into the executable binary.
    4. Support multiple boot agents.
    5. Set LED to PHY mode when card first receives auxilary power.
    6. Enable PXE loading from flash memory.
    7. Disabled the setup for max PCI retry, default to zero.

Version 2.12:
    1. Added ASF support.
                          
Version 2.11:
    1. Fixed Non-Buffer VPD write bug
                          
Version 2.10:
    1. Added flash write support for VPD. 
    2. Added auto negotiation for 5703S.

Version 2.8:
    1. Branched bootcode into several versions to be silicon specific.
    2. Fixed flash timeout problem.

Version 2.7:
    1. Added 5703 support.

Version 2.6:
    1. Added generic loader support.  This is a requirement for ASF support.

Version 2.5:
    1. Fixed the cable unplug/replug problem on PCI-X setting.

Version 2.4:
    1. Fixed cable unplug/replug problem (CQ#1998).

Version 2.3:
    1. Added 100Mbps WOL on A3/B5 boards.
    2. Fixed zero mac address when enabling WOL on fiber card (CQ#2236).

Version 2.2:
    1. Initialize PME Status upon the first time power-up.

Version 2.1:
    1. Fixed bug on WOL.
    2. Temporarily disable BCM5703 support.
    3. Fixed link loss on fiber card.

Version 2.0:
    1. Added WOL support
    2. Added BCM5703 support

Version 1.9:
    1. Added features so that neccessary manufacturing information is 
       stored in the shared memory.  This allows host driver can query 
       these information.

Version 1.8:
    1. Fixed a problem where PXE is not operatable in version 1.7.

Version 1.7:
    1. Added logic for 1.3v and 1.8v voltage source.
    2. Added logic forcing PCI mode.

Version 1.6:
    1. Added BCM5701 support.  
        * Initialize BCM5701 to use PHY LED mode.
        * Initialize BCM5701's PHY to advertise 10/100/1000.
    2. Timer prescaler is now initialized to reflect 66Mhz core clock.

Version 1.5:
    1. Added BCM5700 Fiber support.  

Version 1.4:
    1. Initialize BAR after first reset.

Version 1.3:
    1. Changed so that default manufacturing information now has proper
       power consumption and dissipation.

Version 1.2:
    1. Fixed a problem where firmware has problem accessing PHY registers
       during bootup time for NIC rev.12 and above.

Version 1.1:
    1. Format of ASIC revision ID has been changed.  Changed to generate
       PCI revision ID correctly.  

          ASIC Rev.           PCI Revision ID
          ========            ===============
            B0                     0x10
            B1                     0x11

Version 1.0:
    1. Initialize PHY LED mode based on subsystem vendor ID.
        * Dell Viper LOM (0x1028)  : Triple speed mode (MII 0x10 = 0x0)
        * Other : link/speed mode (MII 0x10 = 0x2)

Version 0.8:
    1. Initialize PHY LED mode based on subsystem device ID.
        * Dell Viper LOM (0x1028)  : Triple speed mode (MII 0x10 = 0x2)
        * Other : link/speed mode (MII 0x10 = 0x0)

Version 0.7:
    1. Initialize PHY (BCM5401) with scripts so that NIC has link after 
         power-on-reset before driver is loaded.

Version 0.6:
    1. Initialize Chip Revision ID in PCI configuration space.

Version 0.5:
    1. Added logic to perform PHY H/W reset.
    2. Initialize VPD delay so that BIOS can access VPD.

Version 0.4:
    Initial release.

